1. Field of the Invention
The present invention relates in general to a memory cell. More particularly, it relates to a flash memory cell and method for fabricating the same to reduce erase voltage and the size of the memory cell.
2. Description of the Related Art
Non-volatile memory, such as flash memory, stores data regardless of electrical power supplied, and reads and writes data by controlling a threshold voltage of a control gate. Conventionally, flash memory includes a floating gate and a control gate. The floating gate stores charge and the control gate reads and writes data. In addition, the floating gate is located under the control gate and is not connected to external circuit, and the control gate connects to the word line. Since flash memory has a high operating speed, it is widely applied for consumer electronics devices, such as digital cameras, mobile phones, personal stereos, and laptops.
FIGS. 1A-1F are cross-sections showing a conventional method of fabricating a split gate flash memory cell.
First, in FIG. 1A, a silicon substrate 10 is provided, and a thin silicon oxide layer 12 is formed thereon serving as a tunnel oxide layer. The tunnel oxide layer 12 can be formed by thermal oxidation and has a thickness of about 80 Å. Next, a polysilicon layer 14 having a thickness of about 1200 Å and a silicon nitride layer 16 having a thickness of about 800 Å are successively deposited on the tunnel oxide layer 12.
Next, in FIG. 1B, a photoresist layer 18 is coated on the silicon nitride layer 16, leaving a portion exposed. Thereafter, the exposed portion of the silicon nitride layer 16 is etched to form an opening 20 exposing the polysilicon layer 14. Thereafter, ion implantation is performed to dope boron ions B into the substrate 10 through the opening 20 to form a channel doping region 22.
Next, in FIG. 1C, the photoresist layer 18 is stripped and thermal oxidation is performed on the exposed polysilicon layer 14 using the remaining silicon nitride layer 16a as a mask to form a thick oxide layer 24 having tipped and thin portions 24a, 24b at its edge in the opening 20.
Next, in FIG. 1D, the remaining silicon nitride layer 16a is removed by wet etching to expose the polysilicon layer 14.
Next, in FIG. 1E, the polysilicon layer 14 is etched by anisotrpically etching, using thick oxide layer 24 as a mask to the tunnel oxide layer 12. The remaining polysilicon layer 14a is used as a floating gate.
Finally, in FIG. 1F, a gate dielectric layer 28, a control gate 30, and source region S/drain region D are formed to finish the fabrication of the split gate flash memory cell.
However, the conventional flash memory cell cannot increase integration of ICs, due to its larger size. Moreover, using the tip portions 24a, 24b of the floating gate 14 to eliminate hot electrons from the floating gate 14 for erasing cannot effectively reduce the erase voltage, such as 10.5 V, due to fewer discharging paths.